1. Field of Invention
The present invention relates to an integrated circuit layout. More particularly, the present invention relates to an integrated circuit layout having a protection circuit loop for protecting integrated circuit devices against electrostatic discharge.
2. Description of Related Art
In the fabrication of an integrated circuit (IC) such as a dynamic random access memory (DRAM) or static random access memory (SRAM), or after the fabrication of a silicon chip, electrostatic discharge (ESD) is one of the major causes of damage leading to integrated circuit failure. For example, anyone walking on a carpeted floor in an environment having a high relative humidity (RH) may generate a few hundred to a few thousand static volts in a human body. If the relative humidity is low, a static voltage of up to ten thousand volts or more may be produced in a human body (in the what is called human-body model (HBM) ESD). Machines for packaging integrated circuits or equipment for testing integrated circuits may also generate anywhere from a few hundred to a few thousand static volts depending on climate and humidity (in the what is called machine model ESD). Similarly, the substrate layer of a semiconductor chip may store up large quantities of electric charges capable of an electrostatic discharge (in the what is called charge-device model (CMD) ESD).
When one of these charged bodies contacts a silicon chip, charges may transfer to the chip in a sudden flow, leading to possible damages to internal circuits and devices. To prevent damages to integrated circuit due to ESD, various types of ESD protection methods are developed. One commonly used method is to build ESD protection hardware devices. In short, an on-chip ESD protection circuit is inserted between the internal circuit and each bonding pad.
FIG. 1 is the layout of a conventional ESD protection circuit. As shown in FIG. 1, an electrostatic discharge (ESD) protection device 10 is inserted between a voltage source VCC1 and a bonding pad 14. Another ESD protection device 12 is inserted between a ground terminal GND1 and the bonding pad 14. The source terminal of a PMOS transistor 16 is connected to a voltage source VCC2. The substrate terminal and the source terminal of the PMOS transistor 16 are connected together. An input resistor Rin 20 is inserted between the gate terminal of the PMOS transistor 16 and the bonding pad 14. The drain terminal of an NMOS transistor 18 is connected to the drain terminal of the PMOS transistor 16. The gate terminal of the NMOS transistor 18 is connected to the gate terminal of the PMOS transistor 16. The substrate terminal and the source terminal of the NMOS transistor 18 are connected together. The substrate resistor Rsub 22 is inserted between another ground terminal GND2 and the ground terminal GND1.
The substrate resistor Rsub 22 is an equivalent resistor between the ground terminal GND1 and the ground terminal GND2. The ESD protection device 10 and the ESD protection device 12 together constitute a group of protection circuits protecting the integrated circuit devices against any HBM ESD or MM ESD at the bonding pad 14.
In FIG. 1, when a CDM ESD of the integrated circuit device occurs, there are two major pathways for releasing electric charges within the substrate to the bonding pad 14. A first pathway I1 starts out at the ground terminal GND2 and travels via the NMOS transistor 18 and the input resistor Rin 20 to the bonding pad 14. A second pathway I2 starts out at the ground terminal GND2 and travels via the substrate resistor Rsub 22 and the ESD protection device to the bonding pad 14. If a large quantity of substrate charges flows via the pathway I1 to the bonding pad 14, the current passes through the gate oxide layer inside the NMOS transistor 18. Thus, the gate oxide layer of the NMOS transistor 18 is likely to be damaged in a CDM ESD.
Accordingly, one object of the present invention is to provide an electrostatic discharge (ESD) protection circuit layout having an additional charge-device model (CDM) ESD protection device within an integrated circuit device so that the integrated circuit device is protected from a CDM ESD.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an electrostatic discharge (ESD) protection circuit layout. The ESD protection circuit layout includes a first ESD protection device, a second ESD protection device, a first CDM ESD protection device, a second CDM ESD protection device, a first charge flow prevention device, a PMOS transistor, an input resistor, an NMOS transistor, a second charge flow prevention device and a substrate resistor. The first ESD protection device is connected to a first voltage source and a bonding pad. The second ESD protection device is connected to a first ground terminal and the bonding pad. The first CDM ESD is connected to a second voltage source and the bonding pad. The second CDM ESD is connected to a second ground terminal and the bonding pad. The first charge flow prevention device is connected to the second voltage source. The source terminal of the PMOS transistor is connected to the first charge flow prevention device. The substrate terminal and the source terminal of the PMOS transistor are connected together. The input resistor is connected to the gate terminal of the PMOS transistor and the bonding pad. The drain terminal of the NMOS transistor is connected to the drain terminal of the PMOS transistor. The gate terminal of the NMOS transistor is connected to the gate terminal of the PMOS transistor. The substrate terminal and the source terminal of the NMOS transistor are connected together. The second charge flow prevention device is connected to the source terminal of the NMOS transistor and a second ground terminal. The substrate resistor is connected to the first ground terminal and the second ground terminal.
The first charge flow prevention device prevents any abnormal charge current from flowing from the second voltage source through the gate oxide layer of the PMOS transistor and damaging the PMOS transistor. The first CDM ESD protection circuit provides a discharging loop so that any abnormal charge current from the second voltage source flows via the first CDM ESD protection device to the bonding pad. Similarly, the second charge flow prevention device prevents any abnormal charge current flowing from the substrate of the integrated circuit device through the gate oxide layer of the NMOS transistor and damaging the NMOS transistor. The second CDM ESD protection circuit provides a discharging loop so that any abnormal charge current from the substrate of the integrated circuit device flows via the second CDM ESD protection device to the bonding pad. The first CDM ESD protection device and the second CDM ESD protection device within the integrated circuit device are normally positioned far away from other internal NMOS and PMOS transistors to reduce possible electrical latch-up.
This invention also provides an alternative electrostatic discharge (ESD) protection circuit layout. The ESD protection circuit layout includes a first ESD protection device, a second ESD protection device, a CDM ESD protection device, a PMOS transistor, an input resistor, an NMOS transistor, a charge flow prevention device and a substrate resistor. The first ESD protection device is connected to a first voltage source and a bonding pad. The second ESD protection device is connected to a first ground terminal and the bonding pad. The CDM ESD is connected to a second ground terminal and the bonding pad. The source terminal of the PMOS transistor is connected to a second voltage source. The substrate terminal and the source terminal of the PMOS transistor are connected together. The input resistor is connected to the gate terminal of the PMOS transistor and the bonding pad. The drain terminal of the NMOS transistor is connected to the drain terminal of the PMOS transistor. The gate terminal of the NMOS transistor is connected to the gate terminal of the PMOS transistor. The substrate terminal and the source terminal of the NMOS transistor are connected together. The charge flow prevention device is connected to the source terminal of the NMOS transistor and the second ground terminal. The substrate resistor is connected to the first ground terminal and the second ground terminal.
The charge flow prevention device prevents any abnormal charge current from flowing from the substrate of the integrated circuit device through the gate oxide layer of the NMOS transistor and damaging the NMOS transistor. The CDM ESD protection circuit provides a discharging loop so that any abnormal charge current from the substrate of the integrated circuit device flows via the CDM ESD protection device to the bonding pad. Such a layout of the CDM ESD protection device within the integrated circuit device is capable of reducing electrical latch-up.
In brief, this invention provides an ESD protection circuit layout. The integrated circuit device includes an additional CDM ESD protection device so that most charges within the integrated circuit device are channeled away via the CDM ESD protection device and ESD protection device. Furthermore, the particular layout of the CDM ESD protection device within the integrated circuit device is capable of reducing electrical latch-up considerably.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.